As the value of statistical process control (SPC) increases in importance when selecting a quality contract assembler, the question becomes, what is good?
High-value contract manufacturers are aiming for Six Sigma quality (3.4 ppm) for solder joints in an automated surface mount line. They key word here is "aiming." Defect levels in an automated surface mount line operating within statistical control tend to vary between 300 to 500 DPMO (defects per million opportunities). This observation tends to be supported in the published literature, including the most exhaustive study published in 2007.
Several articles point to 50 DPMO as world-class performance. An article by Don Revelino of Packard Bell, titled "Achieving Single Digit DPMO in SMT Processes," states that "world-class" is 50 ppm and Packard Bell achieved single-digit DPMO. An article by C. Mangin ("The DPMO: Measuring process performance for world-class quality") also states that approximately 50 or less DPMO is appropriate for continuous assembly of electronics.
In general, wave solder defect rate tends to be an order of magnitude larger than SMT, and manual solder operations tend to be two orders of magnitude larger than SMT. Realizing this, one can see the criticality of designing products that can be manufactured on a SMT line rather than by hand.
Other studies paint a more pessimistic viewpoint of process control over SMT manufacturing. An article by K. Walters ("Improving the Reflow Process with SPC") recommends a minimum Cpk value of 1.33 (600 ppm) for SMT. The report does state that three manufacturers achieved sub-200ppm.
When comparing manufacturers' performance, it is important to ensure that apples are compared to apples. As a general rule of thumb, the number of opportunities should be based on the number of solder joints. In addition, the number of defects should be based on physical defects that have or would lead to failure. Cosmetic defects should not be included. Use IPC610 as the defacto workmanship standard for solder joint acceptance.
So, assume a high-technology board has 10,000 solder joints and 10% of the solder joints are BGA and Flip Chip devices. A defect rate of 50 ppm will result in rework on roughly half of the boards. A defect rate of 20 ppm on a medium technology board with 5,000 solder joints and 5% of solder joints are BGA and FC will result in a rework rate of 10%. For high-volume, low-technology boards containing roughly 500 solder joints with no BGA or FC, it can be seen that on average 1 out of every 100 boards will require rework.
The degree of control required to obtain single-digit DPMO can be appreciated by examining the scenario of one 144-pin quad flat pack (QFP) being misaligned so that all its solder joints are defective. If the manufacturer has a 20 ppm defect rate, the next 7 million solder joints will have to be defect-free before the manufacturer can once again claim a 20 ppm defect rate.